This application claims the priority of Korean Patent Application No. 10-2005-0015041, filed on Feb. 23, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a flash memory device and a method of manufacturing the same, and more particularly, to a split gate flash memory device having a self-aligned control gate and a method of manufacturing the same.
2. Description of the Related Art
Non-volatile semiconductor devices electrically store and erase data and can retain data even when power is turned off. Accordingly, non-volatile semiconductor devices enjoy widespread use in various fields, including portable electronics.
As one type of non-volatile memory device, a split gate flash memory device includes a floating gate (or a storage node) and a control gate that are separated from each other. The floating gate is electrically isolated from the external environment, and stores information using-the characteristic that the current of a memory cell varies according to electron injection (writing) to the floating gate and electron removal from the floating gate (deleting). For example, electron injection to the floating gate is conducted by channel-hot electron injection (HEI), and electron removal from the floating gate is conducted by Fowler-Nordheim (F-N) tunneling through an inter-gate insulating layer that is present between the floating gate and the control gate.
Referring to FIG. 1, a conventional split gate flash memory device includes a floating gate 15 and a control gate 20, which are disposed between a source region 25a and a drain region 25b. The control gate 20 and the floating gate 15 share a portion of a substrate 10, that is, a channel region between the source and drain regions 25a and 25b, respectively, and the control gate 20 surrounds a sidewall and lies on a portion of a top surface of the floating gate 15.
By forming the control gate 20 in this manner, an electric field between the floating gate 15 and the control gate 20 is enhanced, and the problem of punch-through between the source and drain regions 25a and 25b can be solved. Such a split gate flash memory device is disclosed in U.S. Pat. No. 5,067,108.
In the split gate flash memory device, as the control gate 20 is formed by an individual patterning process, an overlap area between the control gate 20 and the channel region varies from chip to chip, lot to lot, or wafer to wafer. Accordingly, cell threshold voltage and device characteristics vary from chip to chip, lot to lot, or wafer to wafer.
Further, since the control gate 20 and the floating gate 15 are formed on the same plane to share the channel region, the cell size of the split gate flash memory device is about 50% larger than that of a stack type flash memory device. Accordingly, it is more difficult to scale down the split gate flash memory device as compared to the stacked flash memory device.